ASTLC6201A - 4-PIXEL 8-BIT TFT-LCD TIMING CONTROLLER WITH LVDS INTERFACE
GENERAL DESCRIPTION
The ASTLC6201A is a TFT-LCD panel controller incorporating the LVDS technology to support displays with resolutions ranging from SXGA (1280 X 1024) to SXGA+ (1400x1050).
The ASTLC6201A accepts host data through two LVDS busses (low-EMI high-throughput interfaces) each made-up of 5 pairs of inputs (i.e. 24-bit data + 1 clock). It then reformats the received image data into a specific format and synchronous timing suitable for driving LCD panel column and row drivers.
With a TTL output interface of 96 lines, the ASTLC6201A supports up to true color panels (24-bit/pixel, 16.7M colors) in 4 pixels/clock mode.
The ASTLC6201A is easily programmable to support several mainstream gate and source drivers and to optimize display quality.
FEATURES
- Supports SXGA (1280 X 1024) and SXGA+ (1400 X 1050) TFT-LCD panel resolutions
- Two 4-channels LVDS input interface (2 pixels x 24-bit)
- Bandwidth per LVDS interface: 40 - 70MHz
- On-chip 96-bit data bus
- 96-lines TTL output interface
- Low power: 3.3V core operation & power-down mode
- Highly programmable: supports mainstream gate and source drivers (e.g. TI57570, KS0674, KS0670, MN838820) and dual edge mode column drive
- Transition Dependent Data Inversion Algorithm (TDDI) transition minimization to reduce power consumption and EMI
- Low profile, 176-pin LQFP, 1.4 mm high package
Block Diagram
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Data Sheet
Available on request
