ASTLC6101A - TFT-LCD TIMING CONTROLLER WITH LVDS-IN AND RSDS-OUT INTERFACES

The ASTLC6101A is a TFT-LCD timing controller that integrates an LVDS receiver and an RSDS (Reduced Swing Differential Signaling) output interface, to support SVGA (800 X 600), XGA (1024 X 768) and Wide XGA (1280 X 768-800) resolutions.

The ASTLC6101A supports 18 or 24 bits/pixel LVDS inputs and transmits 6-bit RSDS data. The LVDS and RSDS are low voltage swing interfaces for low EMI solution.

• Supports SVGA (800 X 600), XGA (1024 X 768), WXGA+ (1280 X 768-800) TFT-LCD panel resolutions
• 4-channels LVDS input interface (18 or 24-bit)
• LVDS interface bandwidth: 25 - 85 MHz
• 6-bit RSDS (Reduced Swing Differential Signaling) output interface for low power and low EMI
• Output RSDS clock up to 85MHz
• Supports DE mode
• Virtual 8-bit color depth in FRC mode
• Build-in self test (BIST) mode
• Low power 3V core operation
• Low profile, 64-pin TQFP package (10mm X 10mm body size)

Available on request